1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise highly capacitive gate structures including a metal-containing electrode and a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface defined by highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, at least at the interface to the gate insulation layer, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, even at an increased thickness, compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. As the threshold voltage of the transistors is significantly affected by the work function of the gate electrode material that is positioned near and in contact with the gate dielectric material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material in the channel region that forms an interface with the gate dielectric material, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also present an additional complex process step, which, however, may avoid complex processes for adjusting the work function and thus the threshold voltages in a very advanced process stage.
It turns out, however, that the manufacturing sequence of forming the threshold adjusting semiconductor alloy may have a significant influence on threshold variability and other transistor characteristics, as will be described in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 above which is formed a silicon-based semiconductor material 102 having an appropriate thickness for forming therein and thereabove transistor elements. Moreover, an isolation structure 102C is formed in the semiconductor layer 102, thereby laterally delineating active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is to be created in order to form PN junctions for one or more transistor elements. In the example shown, the active region 102A corresponds to a P-channel transistor having a corresponding well implantation species, such as an N-type species, incorporated therein, while the active region 102B represents an N-channel transistor and thus includes a P-type well dopant species. Additionally, a mask layer 103 is formed in the active regions 102A, 102B in the form of a silicon dioxide material, which may be grown on the active regions 102A, 102B. Furthermore, an etch mask 104 is provided such that the active region 102B is covered, while the active region 102A, i.e., the mask layer 103 formed thereon, is exposed to an etch ambient 105.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. First, the isolation structure 102C is formed on the basis of well-established lithography, etch, deposition, planarization and anneal techniques in which, for instance, a trench is formed in the semiconductor layer 102 on the basis of a lithography process, which is subsequently to be filled with an appropriate insulating material, such as silicon dioxide, silicon nitride and the like. After removing any excess material and planarizing the surface topography, the further processing is typically continued by performing a plurality of implantation sequences using an appropriate masking regime in order to introduce the required dopant species for generating the basic well doping concentration in the active regions 102A, 102B corresponding to the type of transistors to be formed therein and thereabove. After activating the dopant species and re-crystallizing implantation-induced damage, the further processing is continued by forming the mask layer 103 on the basis of an oxidation process, followed by the deposition of a mask material, such as a resist material, that is subsequently patterned into the mask 104 by well-established lithography techniques. Next, the etch process 105 is performed, for instance by using a wet chemical etch recipe based on, for example, hydrofluoric acid (HF), which may remove silicon dioxide material selectively with respect to silicon material. During the etch process 105, therefore, a material loss in the isolation structures 102C may also occur with a more or less pronounced degree, depending on the process parameters of the etch process 105.
FIG. 1b schematically illustrates the semiconductor device 100 after the above-described process sequence and after removal of the etch mask 104 (FIG. 1a). As described before, an increased surface topography may be created during the preceding etch process since, typically, a portion of the sidewalls 102S of the active region 102A may be exposed, depending on the required over-etch time for reliably removing the mask layer 103 (FIG. 1a) from the active region 102A.
FIG. 1c schematically illustrates the semiconductor device when exposed to a further process ambient 106, which may typically be established in a deposition reactor for performing a selective epitaxial growth process. For example, elevated temperatures may be applied and appropriate reactive gas components may be used in order to remove any contaminants and oxide residues from the exposed surface areas of the active region 102A, for instance in the form of a native oxide and the like. Thus, during the process 106, additional material of the isolation structures 102C, as indicated by 102R, may be removed and also the thickness of the mask layer 103 still covering the active region 102B may be reduced. Consequently, the process 106 may further contribute to an increased exposure of the sidewall surface 102S.
FIG. 1d schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 108, in which process parameters are selected in accordance with well-established recipes such that a significant material deposition is restricted to the exposed active region 102A, while a material deposition on dielectric surface areas, such as the isolation structure 102C and the mask layer 103 is strongly suppressed. During the selective epitaxial growth process 108, a silicon/germanium alloy 109 may, therefore, be selectively formed on the active region 102A wherein, due to the exposed sidewall surface areas 102S, a pronounced material deposition may also occur above the isolation structure 102C. Generally, the material composition of the alloy 109, as well as a thickness thereof, have a strong influence on the finally obtained threshold voltage of the P-channel transistor to be formed in and above the active region 102A. For example, in sophisticated applications, a target thickness of the silicon/germanium alloy 109 may be approximately 10 nm, wherein a thickness variation of several percent may result in a significant variability of the finally achieved transistor characteristics. Thus, due to the exposed sidewall surface areas 102S, a different deposition behavior may occur during the process 108 at the periphery of the active region 102A compared to a central region, which may contribute to a significant thickness non-uniformity.
FIG. 1e schematically illustrates the semiconductor device 100 when exposed to an etch ambient 110 in which the mask 103 (FIG. 1d) is removed selectively with respect to the active regions 102A, 102B. For this purpose, hydrofluoric acid may be used or any other appropriate selective etch chemistry so as to not unduly remove material of the active regions 102A, 102B. On the other hand, during the etch process 110, the resulting surface topography may further be increased by additionally removing material of the isolation structures 102C, thereby contributing to a further pronounced topography at a peripheral area 102P around the active region 102A. Additionally, upon removing the mask layer 103, the final difference in the height level between the active region 102A, which comprises the silicon/germanium alloy 109, and the active region 102B may further be increased, which may also result in an increased degree of complexity during the further processing. That is, after the etch process 110, appropriate gate dielectric materials, which typically comprise a high-k dielectric material, are formed on the basis of oxidation in combination with deposition techniques, followed by the deposition of a complex gate electrode stack, which may typically comprise a metal-containing cap layer for the high-k dielectric material and one or more additional materials. Hence, the different height levels may also result in a certain degree of non-uniformity of the resulting gate stack. Consequently, during the complex patterning sequence for forming gate electrode structures in accordance with a desired critical gate length dimension, the difference in the height levels between the active regions 102A and 102B may result in a different gate length. Furthermore, the previously deposited silicon/germanium alloy 109 may have an intrinsic thickness variability due to the material growth at the exposed sidewall surface areas 102S, which may result in a corresponding variation along the transistor width direction, i.e., the direction perpendicular to the drawing plane of FIG. 1e. Due to the strong dependence of the resulting threshold voltage on the material characteristics of the silicon/germanium alloy 109, a pronounced variability of the threshold voltage along the transistor width direction may also be observed, thereby resulting in a high degree of transistor variability and thus in a less reliable and less predictable transistor operation.
In some sophisticated approaches, the threshold variability of the P-channel transistor is reduced by recessing the active region 102A prior to performing the selective epitaxial growth process in order to avoid or at least suppress the growth of the silicon/germanium alloy 109 at the exposed sidewall surfaces 102S. In this manner, more uniform growth conditions may be achieved across the entire surface of the active region 102A, thereby also providing enhanced uniformity of the material composition and layer thickness of the resulting channel alloy 109. Consequently, in a manufacturing stage as shown in FIG. 1b, the active region 102A may be recessed while the active region 102B is covered by the mask 103.
It has been observed, however, that, although a superior uniformity of the resulting threshold voltage is achieved by applying the latter approach compared to former strategy due to the superior uniformity of the silicon/germanium alloy, the latter approach results in a general increase of the threshold voltage of several tens of mV compared to the former approach, which may thus make the concept of recessing the active region less than desirable, unless the change of threshold voltage may be efficiently compensated.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.